The present invention relates, generally, to the field of microelectronic packaging, and more particularly relates to provision of a compliant interface between microelectronic elements such as a semiconductor chip and substrate.
Designers and manufacturers of electronic devices are continually searching for ways to reduce the size of electronic components. Some recent developments involve the use of solder connections for electrically interconnecting semiconductor chips to printed circuit boards (xe2x80x9cPCBxe2x80x9d) in order to use the space on the PCB more efficiently. Solder connections have proven to be somewhat effective; however, the differences in thermal expansion and contraction (xe2x80x9cthermal mismatchxe2x80x9d) between the semiconductor chip and the PCB places a great amount of stress on the solder connections and may adversely effect the integrity of the numerous solder bonds required to make an electrical connection. Additionally, warpage of either the semiconductor chip or the PCB may also have a negative effect on the integrity of the solder connections.
There have been a number of prior art solutions attempting to reduce the effects of stress on solder connections. One solution teaches embedding wires within each solder column to reinforce the solder (U.S. Pat. No. 4,642,889). Another solution includes wrapping wire around the outside of the solder, and a further solution includes providing a combination of solder and high-lead solder (U.S. Pat. No. 5,316,788). Still other prior art solutions make use of an underfill material disposed between the semiconductor chip and the supporting substrate which allows the stress caused by the thermal mismatch to be more uniformly spread out over the entire surface of the solder connection. All of these prior art solutions are aimed at improving the reliability of solder connections; however, each of these solutions encounters significant problems, such as insufficient compliancy between the semiconductor chip and the PCB.
Several inventions, commonly assigned to the assignee of the present invention, deal effectively with the thermal mismatch problems described above. For example, U.S. Pat. No. 5,148,266 (xe2x80x9cthe ""266 patentxe2x80x9d) discloses improvements in semiconductor chip assemblies and methods of making the same. In certain embodiments of the ""266 patent, a semiconductor chip can be connected to a substrate using a sheet-like, and preferably flexible, interposer. In this embodiment, the interposer overlies the top, contact-bearing surface of the chip. A first surface of the interposer faces towards the chip whereas a second surface faces away from the chip. Electrical terminals, which can be bonded to a substrate, are provided on the second surface of the interposer, and the interposer is provided with apertures extending through it. Flexible leads extend through the apertures, between the terminals on the second surface of the interposer and the contacts on the chip. Because the terminals are movable relative to the contacts on the chip, the arrangements described in the ""266 patent provide excellent resistance to differential expansion of the chip relative to the substrate caused by thermal mismatch or thermal cycling. The interposer disclosed in the ""266 patent may also include a compliant layer disposed between the terminals and the chip.
Commonly assigned U.S. Pat. No. 5,477,611 (xe2x80x9cthe ""611 patentxe2x80x9d), the disclosure of which is incorporated herein by reference, discloses a method for creating an interface between a chip and chip carrier including spacing the chip a given distance above the chip carrier, and introducing a liquid in the gap between the chip and carrier. Preferably, the liquid is a curable material which is cured into a resilient layer such as an elastorner after its introduction into the gap. In a preferred embodiment, the terminals on a chip carrier are planarized or otherwise vertically positioned by deforming the terminals into set vertical locations with a plate, and a liquid is then cured between the chip carrier and chip.
Co-pending, commonly assigned U.S. patent application Ser. No. 08/365,699 entitled xe2x80x9cCompliant Interface for a Semiconductor Chip and Method Thereforxe2x80x9d filed Dec. 29, 1994 (xe2x80x9cthe ""699 applicationxe2x80x9d), the disclosure of which is incorporated herein by reference, discloses a method of fabricating a compliant interface for a semiconductor chip, typically comprised of a compliant encapsulation layer having a controlled thickness. In certain preferred methods according to the ""699 application, a first support structure, such as a flexible, substantially inextensible dielectric film (xe2x80x9cdielectric elementxe2x80x9d), is provided. A resilient element, such as a plurality of compliant pads, is attached to a first surface of the first support structure. Attaching the compliant pads to the first support structure may be accomplished in a number of different ways. In one embodiment, a stencil mask having a plurality of holes extending therethrough is placed on top of the first surface of the support structure. The holes in the mask are then filled with a curable liquid, such as a silicone. After the mask has been removed, the curable liquid is at least partially cured to form an elastomer, such as by heating or by exposure to ultraviolet light. Thus, there is provided an assembly which includes a plurality of compliant pads having channels between adjacent pads.
In a further embodiment of the ""699 application, the assembly including the plurality of compliant pads is used with a second support structure such as a semiconductor chip having a plurality of contacts on a first surface. The first surface of the chip is abutted against the plurality of compliant pads and the contacts are electrically connected to a corresponding plurality of terminals on a second side of the support structure. Typically, the first surface of the chip is pressed against the array of compliant pads by a platen engaged with the terminals, thereby assuring the planarity of the first support structure, or flexible dielectric film. A compliant filler such as a curable liquid is then injected into the channels between the chip and the support structure and around the compliant pads while the chip and support structure are held in place. The filler may then be cured to form a substantially uniform, planar, compliant layer between the chip and the support structure. Preferred embodiments of the ""699 application provide a compliant, planar interface which effectively accommodates for the thermal mismatch between the chip and a supporting substrate, thereby alleviating much of the stress on the connections therebetween. Further, the combination provides an effective encapsulation barrier against moisture and contaminants.
In the methods of fabricating a compliant interface for a semiconductor chip discussed above, the resilient element or compliant pads may be bonded to either the semiconductor chip or the dielectric element using an adhesive.
Commonly assigned U.S. Pat. No. 5,548,091 describes other methods of bonding compliant elements to the chip and support structure using adhesives. In certain preferred methods according to the ""091 patent, a support structure such as a dielectric film is provided with a prefabricated compliant layer. The compliant layer in turn has an adhesive on its surface remote from the dielectric film. The semiconductor chip is placed in contact with the adhesive, and the adhesive is activated to bond the chip to the compliant layer. The adhesive may be provided in a non-uniform layer to facilitate release of air during the bonding process and thus prevent void formation. Known adhesives tend to delaminate from the resilient element under the extreme stresses of temperature and humidity and also under stress of extreme thermal mismatch. Accordingly, still further improvements directed toward providing a resilient element that can be more effectively bonded to microelectronic elements using known adhesives would be desirable.
The present invention is directed to the desired improvements discussed above.
One aspect of the present invention provides a method of making microelectronic packages. A method in accordance with this aspect of the invention includes the step of providing a first microelectronic element having electrically conductive parts, providing a resilient element having one or more intermediary layers at surface regions of the resilient element which are capable of being wetted by adhesives and assembling the resilient element in proximity with the first microelectronic element. The resilient element may comprise fibrous material, a fibrous mesh or voids at the one or more intermediary layers, thereby providing the resilient element with one or more surface regions capable of being wetted. The resilient element may be a unitary compliant pad having a generally square or rectangular shape or may be in the form of a plurality of compliant pads (e.g., a matrix of pads) with adjacent pads defining channels therebetween, as described in the ""699 Application or in co-pending, commonly assigned U.S. patent application entitled xe2x80x9cTransferable Compliant Pads for Packaging of a Semiconductor Chip and Method Therefor.xe2x80x9d
The method also includes the steps of providing a second microelectronic element and assembling the resilient element in proximity with the second microelectronic element. An adhesive is provided in contact with at least one of the intermediary layers of the resilient element and at least one of the microelectronic elements and the adhesive is cured while it remains in contact with at least one of the intermediary layers of the resilient element and at least one of the microelectronic elements. After curing, the adhesive bonds to the intermediary layer at the surface regions of the resilient element. After electrically connecting the microelectronic elements, a liquid encapsulant may be applied to, inter alia, protect the electrical connection and create a compliant layer.
This aspect of the invention incorporates the realization that known adhesives tend to delaminate from the resilient element under the stress of temperature, humidity and thermal cycling. Although the present invention is not limited by any theory of operation, it is believed that these difficulties result from the non-wetting properties of silicone elastomer, and/or the lack of surface irregularities on the resilient element for engaging and intermeshing with the adhesive. In some embodiments adhesives have difficulty wetting to some fully cured resilient elements and thus the adhesives are unable to effectively bond therewith. As a result, there is only weak adhesion between the resilient element and the adhesive resulting in a relatively weak bond between the resilient element and the microelectronic elements. This could result in the failure of the semiconductor chip package during operation. Thus, by providing a resilient element having one or more intermediary layers capable of being wetted with an adhesive, the difficulties associated with creating an effective bond between the surface of the resilient element and the adhesive are substantially eliminated. In preferred embodiments of the present invention, the concept of wetting with an adhesive includes classical chemical wetting whereby the resilient element and the adhesive form a chemical bond and other forms of wetting whereby the adhesive interpenetrates with a fibrous material or the intermediary layer.
In accordance with one embodiment, the resilient element is formed on a dielectric film and has a first intermediary layer. The resilient element is then assembled to a semiconductor chip using a thermosetting adhesive layer disposed between a first intermediary layer of the of the resilient element and the face of the semiconductor chip and is cured while it remains in contact with the first intermediary layer so that the adhesive effectively bonds to the first intermediary layer which in turn bonds the resilient element to the semiconductor chip.
Prior to the curing step, the adhesive typically is provided in a first solid, non-tacky state; however, during the curing step the adhesive is momentarily converted into a fluid state whereby the adhesive is capable of engaging and intermeshing with the fibrous material, fibrous mesh, and/or voids present at the first intermediary layer of the resilient element. Upon further curing of the adhesive, the adhesive transforms from the fluid state to a second solid state, whereby the first intermediary layer is bonded to the front face of the semiconductor chip. After the adhesive has been fully cured, the electrically conductive parts of the dielectric film and the semiconductor chip may be bonded to one another to form electrical interconnections. It is also contemplated that the electrically conductive parts may be bonded together before the adhesive is cured.
Another aspect of the present invention provides methods of making resilient elements having one or more intermediary layers capable of being wetted by an adhesive. The resilient elements which are provided by these methods typically comprise a cured silicone elastomer such as the silicone elastomer SYLGARD(trademark) 577 provided by Dow Coming and can be used in the processes described above, and in other processes for fabricating microelectronic packages. In one preferred embodiment according to this aspect of the invention, a layer of fibrous material such as paper is provided at one or more surface regions of a curable elastomer. In another embodiment, a fibrous mesh or pad is provided at one or more surface regions of a curable elastomer. In a further embodiment, a fibrous material is mixed with or blended into a curable elastomer for providing a curable elastomer having one or more intermediary layers. The fibrous material may include loose fibers such as cellulose fibers, cotton fibers, or synthetic fibers such as nylon or polypropylene. In this embodiment, the fibrous material is mixed with the mass of a curable elastomer so that some of the fibers protrude from the mass after the mixing step. The mass is then subjected to a curing process, such as exposing the mass to heat or ultraviolet light, whereby the mass is transformed into the resilient element having one or more irregular surface regions.
The resilient element provided by the above described methods can be used with an adhesive to bond the resilient element to a microelectronic element. After curing of the adhesive, the adhesive engages and intermeshes with the fibrous material, irregularities and/or voids present at the surface of the resilient element to create a strong bond between the resilient element and the adhesive and avoids the delamination problems described above. In an alternative embodiment, a mixture comprising of mass of a curable elastomer and loose fibers dispersed throughout the mass is introduced between a microelectronic element and a platen. The mixture is then cured to provide the resilient element having one or more irregular surface regions.
A further embodiment of the present invention provides methods of making a resilient element having one or more intermediary layers capable of being wetted whereby the intermediary layers comprise voids provided at one or more surface regions of the resilient element. According to this embodiments a mass of a curable elastomer is provided in a liquid or a semi-liquid form and an agent, such as a gas, is introduced into the mass to form gas bubbles in the curable elastomer. The gas may be introduced into the curable elastomer by injecting the gas into the curable elastomer or by mixing a blowing agent into the curable elastomer and generating the gas by converting the blowing agent to gaseous form. The introduction of the gas into the mass provides one or more intermediary layers comprising of an open cell foam having irregularities such as gaps or voids at one or more surface regions of the resilient element. The voids at the surface regions are capable of receiving, wetting and intermeshing with the adhesive described above while the adhesive is in a fluid state so that when the adhesive transforms back to a solid state the adhesive is intermeshed with the voids to create a strong bond between the resilient element and the adhesive, which in turn creates a strong bond between the resilient element and a microelectronic element.
The present invention also includes embodiments whereby storage liners are placed over the one or more intermediary layers of the resilient element to improve the shelf-life of the resilient element and prevent the resilient element from becoming contaminated.
The present invention includes further embodiments whereby the adhesive is provided at the one or more intermediary layers of the resilient element rather than being provided on microelectronic elements. In one preferred embodiment, a resilient element having first and second intermediary layers is provided by the methods described above. Adhesive layers are then provided over the first and second intermediary layers and storage liners are provided over the adhesive layers to preserve the resilient element while it is in storage. When the resilient element is to be assembled as part of a microelectronic package, the storage liners are removed and the resilient element/adhesive subassembly is assembled between microelectronic elements.
The foregoing and other objects and advantages of the present invention will be better understood from the following detailed description of a preferred embodiment taken together with the attached figures.